In the field of control, systems in which data is collected from one or more input/output units via a network, so that one controller can monitor the input state of the input/output units arranged at positions away from the controller by several to several hundreds of meters, and systems for distributing the control data to the input/output units via the network to-control the output state have been widely put into practical use.
Conventionally, the number of inputs and outputs per input/output unit (one unit is equal to one bit) ranges from 8 to 64. However, based on user demands, the number of inputs and outputs per input/output unit ranges from 1 to 8, in some recent input/output units. The network to be used is referred to as a field network for the former case, and as a sensor/actuator network for the latter case, due to the background of establishment in the market and a difference in the number of inputs and outputs of the input/output units. The sensor/actuator network. The outline is explained with reference to FIG. 9. In the specification, a network in which the number of inputs and outputs of the input/output unit is 8 or more is referred to as the field network, and a network in which the number of inputs and outputs of the input/output unit is less than 8 are referred to as the sensor/actuator network.
FIG. 9 is a conceptual diagram when the field network and the sensor/actuator network are hierarchical. In FIG. 9, a controller 110 is connected to a field network 111 having a length of from several tens to several thousands of meters, and m groups (m=1 to M) are connected to the field network 111. A transfer apparatus 121m connected to the field network 111 is arranged in the group m. A plurality of input/output units 122mn (n=1 to N) are connected to the transfer apparatus 121m via a sensor/actuator network 112m having a length of from several to several hundreds of meters. That is, the transfer apparatus 121m transmits to the controller 110, input state data received from the input/output units 122mn belonging to its own group, and also distributes control data received from the controller 110 to the input/output units 122mn of its own group.
A case that the controller collects data indicating the input state from one or more input/output units will be explained next, with reference to FIGS. 10 to 21. FIG. 10 is a diagram to explain data collection from the input/output unit in one group shown in FIG. 9. FIG. 10 is a diagram to explain a case that the input/output units 122mn in the group m creates a transmission frame 123mn including input state data to transmit the data to the sensor/actuator network 112m, and the transfer apparatus 121m in the group m creates a transmission frame 123m addressed to the controller 110 from the transmission frame. 123mn received from the sensor/actuator network 112m, to transmit the data to the field network 111.
The transmission frame 123mn is a bit string including a header field 71, a data field 72, and a check field 73. The transmission frame 123m is a bit string including a header field 75, a data field 76, and a check field 77. The configuration of such a transmission frame is generally used in serial communication, and the similar configuration is used in the Non-patent Literatures 1 to 6. The correspondence between the bit arrangement in the data field and the input/output ports of the input/output units is determined fixedly such that the least significant bit (LSB) represents the state of the 0-th input/output port.
The unit in the data field 76 in the transmission frame specified in the Non-patent Literatures 1, 2, and 5 is 1 byte. The unit in the data field 76 in the transmission frame specified in the Non-patent Literature 4 is 4 or 2 bytes. The unit in the data field 72 in the transmission frame specified in the Non-patent Literature 3 is 0.5 byte (4 bits are fixed). The unit in the data field 72 in the transmission frame specified in the Non-patent Literature 6 is 0.5 byte, 1 byte, or 2 bytes.
In FIG. 10, therefore, it is assumed that the unit in the data field 72 in the transmission frame 123mn to be transmitted to the sensor/actuator network 112m by the input/output unit 122mn is 1 byte. That is, the data field 72 in the transmission frame 123mn includes 8 bits of from bit b0 to bit b7. The first bit b0 on the header field 71 side is the least significant bit (LSB), and the eighth bit b7 on the check field 73 side is the most significant bit (MSB). The one-to-one correspondence between the bit position and the input/output port in the data field 72 is determined fixedly.
The unit in the data field 76 in the transmission frame 123m to be transmitted to the field network 111 by the transfer apparatus 121m is assumed to be 1 byte. A bit string 113m stored in the data field 76 includes 2×L bits (L is a multiple of 4), wherein the first bit on the header field 75 side is the least significant bit (LSB), and the last bit on the check field 77 side is the most significant bit (MSB). In FIG. 10, the input/output unit 122mn has two input ports mnP0 and mnP1, and hence, 2 bit data from the respective input/output units 122mn is stored in the data field 76. In other words, the first bit and the second bit are data from an input/output unit 122m1, and the third bit and the fourth bit are data from an input/output unit 122m2.
The input/output unit 122mn includes an input port mnPk to which an input 125mnk (in the example, k=0, 1) is connected, a storage unit that stores a data fragment 126mn indicating the state of the input port mnpk, and a transmitter 127mn that stores the data fragment 126mn in the data field 72 in the transmission frame 123mn, and transmits the data to the sensor/actuator network 112m. In the data fragment 126mn, a value (“0” or “1”) of the input port mnP0 is stored in the bit b0, and a value of the input port mnP1 is stored in the bit b1. Because there is no corresponding input port in the bits b2 to b7, a value 0 is stored.
In the input/output unit 122mn, the input port mnPk monitors the input state of the input 125mnk (k=0, 1). The input port mnPk outputs a value 1 to the data fragment 126mn when the input state of the input 125mnk is ON, and outputs a value 0 to the data fragment 126mn when the input state of the input 125mnk is OFF. In the example shown in the figure, the input state of the input 125mn0 is ON, and the input state of the input 125mn1 is OFF. Therefore, “10000000” is stored in the bits b0 to b7 of the data fragment 126mn. The transmitter 127mn stores the data fragment 126mn in the data field 72 in the transmission frame 123mn, and transmits the data to the transfer apparatus 121m. 
The transfer apparatus 121m receives the transmission frame 123mn, stores the data derived from the input port mnPk respectively stored in the data field 72 of the transmission frame 123mn (n=1 to N), in the (2×(m−1)+1)th bit to the (2×m)th bit, respectively, to generate the transmission frame 123m, and transmits the transmission frame 123m to the controller 110.
The processing content for creating the transmission frame 123m addressed to the controller 110 from the transmission frame 123mn received by the transfer apparatus 121m from the input/output units 122mn will be specifically explained with reference to FIGS. 11 and 12. FIG. 11 illustrates a process in which the transfer apparatus 121m uses an 8-bit microcomputer to extract, from the transmission frame 123mn, the respective data of 64 (the number of stations N=64) input/output units 122mn having 2 as the number of inputs, and embeds the respective data in corresponding bit positions in the bit string 113m of the transmission frame 123m. FIG. 12 is a diagram for specifically explaining the processing content related to part “a” shown in FIG. 11.
In FIG. 11, the transfer apparatus 121m defines constants in a constant defining section, declares variables in a variable defining section, and obtains the value in the data field 72 in the transmission frame 123mn according to a function get_sensor_actuator_network_data( ) into an array variable d123mn. The value of an array variable d123mn[0], which has stored the data from an input port 125m1k (k=0, 1) of the input/output unit 122m1 having a station number 1, is stored in a variable d0. Further, the value of an array variable d123mn[1], which has stored the data from an input port 125m2k (k=0, 1) of the input/output unit 122m2 having a station number 2, is stored in a variable d1. The value of the variable d1 is shifted by 2 bits leftward based on the station number n=2, to perform OR operation of the variable d1 and the variable d0. The value of an array variable d123mn[2], which has stored the data from an input port 125m3k (k=0, 1) of an input/output unit 122m3 having a station number 3, is then stored in the variable d1, and the value of the variable d1 is shifted by 4 bits leftward based on the station number n=3, to perform OR operation of the variable d1 and the variable d0.
The value of an array variable d123mn[3], which has stored data from an input port 125m4k of an input/output unit 122m4 having a station number 4, is stored in the variable d1, and after shifting the value of the variable d1 by 6 bits leftward based on the station number n=4, the logical sum of the variable d1 and the variable d0 is stored in an array variable d123m. Likewise, processing is performed for storing data d123mn[nsub] (nsub=i+0 to i+3, i is a multiple of 4) for four stations together in d123m[i] until i becomes N−4, to finish generation of data d123m, and the data stored in the array variable d123m is transmitted to the controller 110 according to a function set_field_network_data ( ).
In FIG. 12, the processing for the part “a” shown in FIG. 11 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C). As shown in column (C), as for the number of clock cycles required when the microcomputer executes a command, if one clock cycles is required for one command, and when the data of 64 input/output units is stored together, a total of 2240 clock cycles are required for the processing of 16 lines in part “a” shown in FIG. 11, and 976 clock cycles, which is about 44% of 2240 clock cycles, are required for the bit shift processing.
A process in which the input/output unit 122mn determines the data fragment 126mn from the input 125mnk will be explained specifically with reference to FIGS. 13 to 15. FIGS. 13 and 14 illustrate a process in which the input/output unit 122mn uses an 8-bit microcomputer to determine the data fragment 126mn from the input 125mnk. FIG. 13 is a diagram to explain an instance in which the input port has the same address, and FIG. 14 is a diagram to explain an instance in which the input port has a different address. FIG. 15 is a diagram for explaining the details of a process related to part “b” shown in FIG. 14.
In FIG. 13, the input/output unit 122mn defines constants in a constant defining section, declares variables in a variable defining section, and then the input 125mnk is fetched from the input port mnPk (k=0, 1) into a variable mnP, which is just the data fragment 126mn according to a function get_port_status( ). An AND operation of the variable mnP and a constant 0x03 (03 in hexadecimal format) is performed so that bits other than the input port mnPk become 0, the result of the AND operation is stored in the variable d123mn, and also in the data fragment 126mn according to a function set_sensor_actuator_network_data( ).
In FIG. 14, the input/output unit 122mn defines constants in a constant defining section, declares variable in a variable defining section, and then the input 125mnk is fetched from the input port mnPk (k=0, 1) into a variable mnP0 and mnP1 respectively according to a function get port status( ). Then, if mnP0≠0 then an OR operation of variable 123mn, which is iust the data fragment 126mn, and variable mnP0on is performed, and if mnP1≠0 then an OR operation of variable 123mn and a variable mnP1on is performed. The result of the OR operations are stored in the variable d123mn according to set sensor actuator network data( ) to transmit the data to transfer apparatus 121m. 
In FIG. 10, it is assumed that the input 125mn0 is ON, and the input 125mn1 is OFF. The details of the process in this case are shown in FIG. 15. In FIG. 15, the process in the part “b” shown in FIG. 14 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C).
In column (B) in FIG. 15, at step (1), a value 0x00 (00 in hexadecimal number) is stored in the variable d123mn. At step (2), the value in the variable mnP0 derived from the input 125mn0 is stored in register a. In this example, because the input 125mn0 is ON, a value 0x01 is stored in the register a. At step (3), because the value of the register a is 0x01, control proceeds to step (4). At step (4), the value of the variable d123mn is stored in the register a. At step (5), the value 0x01 of the variable mnP0on is stored in register b. At step (6), OR operation of the values of the register b and the register a is performed, to change the value of the register a to 0x01. At step (7), the value of the register a is stored in the variable d123mn. In this example, the value 0x01 is stored in the variable d123mn. At step (8), the value in the variable mnP1 derived from the input 125mn1 is stored in the register a. In this example, because the input 125mn1 is OFF, the value 0x00 is stored in the register a. At step (9), because the value of the register a is 0x00, the processing for the part “b” shown in FIG. 14 finishes, and processing proceeds to a command subsequent to step (13), so that the value 0x01 of the variable d123mn is passed to the subsequent step.
As shown in column (C) in FIG. 15, as for the number of clock cycles required when the microcomputer executes the command, if one clock cycle is required for one command, a total of 9 clock cycles is required for the process of 3 lines in part “b” shown in FIG. 14.
FIG. 16 is a diagram for explaining a configuration of a conventional hierarchical data collection system and contents of the process executed by the transfer apparatus. FIG. 16 illustrates a system in which the controller 110 that controls the whole system collects input state data from three input/output units 250q (q=A, B, C) via a transfer apparatus 211, to monitor the state of an object to be controlled. The transfer apparatus 211 is connected to the controller 110 via the field network 111, and to the input/output units 250q via the sensor/actuator network 112. The configuration and contents of the process of the input/output units 250q shown in FIG. 16 are shown in FIGS. 17 to 19.
In FIG. 16, the transfer apparatus 211 includes a receiver 224 that receives a bit string 114q from three input/output units 250q (q=A, B, C) respectively, an operation unit 223 that receives the data fragment 132q from the receiver 224, a transmission buffer 222 that stores data fragments 228a and 228b generated by the operation unit 223 as a low-order data fragment 222a and a high-order data fragment 222b respectively, and a transmitter 221 that stores the low-order data fragment 222a and high-order data fragment 222b stored by the transmission buffer 222 in a bit string 113 and transmits the bit string 113 to the controller 110.
In FIG. 16, the bit string 113 includes 16 bits. The positions of the LSB and the MSB in the bit string 113 are displayed in the opposite direction to those shown in FIG. 10, and the LSB is at the right end. In the bit string 113, the first and the second bits on the lowest order side indicate the data 141A transmitted by the input/output unit 250q (q=A). The third to the sixth bits indicate the data 141B transmitted by the input/output unit 250q (q=B). The seventh to the tenth bits indicate the data 141C transmitted by the input/output unit 250q (q=C). The eleventh to the highest order sixteenth bit are not used.
The operation unit 223 stores a data fragment 132A received from the receiver 224 as a data fragment 131A in a register 223a. The operation unit 223 shifts the data fragment 132B received from the receiver 224 by 2 bits leftward, which is a direction toward the MSB, to obtain a data fragment 131B, and stores the data fragment 131B in a register 223c. The operation unit 223 provides a data fragment 132C received from the receiver 224 to two shift registers 223d and 223f. The shift register 223d shifts the data fragment 132C by 6 bits leftward to generate a data fragment 131Ca, and stores the data fragment 131Ca in a register 223e. On the other hand, the shift register 223f shifts the data fragment 132C by 2 bits rightward to generate a data fragment 131Cb, and designates the data fragment 131Cb as a data fragment 228b. OR operation of the data fragments stored in the registers 223a, 223c, and 223e is performed to generate a data fragment 228a. 
The transmission buffer 222 stores the data fragment 228a as the low-order data fragment 222a, and the data fragment 228b as the high-order data fragment 222b. The transmitter 221 stores the low-order data fragment 222a and the high-order data fragment 222b in the bit string 113. In the bit string 113, therefore, 2-bit data 141A transmitted by the input/output unit 250q (q=A), 4-bit data 141B transmitted by the input/output unit 50q (q=B), and 4-bit data 141C transmitted by the input/output unit 50q (q=C) are arranged, without a gap, from the LSB toward the MSB.
As shown in FIGS. 17 to 19, the input/output unit 250q includes a data generator 253qk that generates a data fragment 158qk from an input 154qk (k=0 to 3), a data fragment generator 256q that generates a data fragment 157q from the data fragment 158qk, a data fragment storage unit 252q that stores the data fragment 157q, and a transmitter 251q that transmits the data fragment 157q as the bit string 114q to the transfer apparatus 211.
When the input 154qk is ON, the data generator 253qk sets a bit value in the (k+1)-th bit from the LSB in the data fragment 158qk to “1”, and when the input 154qk is OFF, sets a bit value in the (k+1)-th bit from the LSB in the data fragment 158qk to “0”. The data fragment generator 256q then performs OR operation of all the data fragments 158qk, having the same value of q, to generate the data fragment 157q. 
An operation of the conventional data collection system having the above configuration will be explained. In the input/output unit 250A shown in FIG. 17, because an input 154A0 is ON, a data generator 253A0 generates data “11111111”, in which all eight bits are “1”, and performs AND operation of the data and an 8-bit constant “00000001” in which the first bit at the LSB is “1” and other bits are “0”, to generate a data fragment 158A0 (“00000001”) having an 8-bit length, in which the first bit at the LSB is “1” and other bits are “0”.
Because an input 154A1 is OFF, a data generator 253A1 generates data “00000000”, in which all eight bits are “0”, and performs AND operation of the data and an 8-bit constant “00000010” in which the second bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158A1 (“00000000”) having an 8-bit length, in which the second bit from the LSB is “0” and other bits are “0”.
Next, a data fragment generator 256A performs OR operation of the data fragment 158A0 and the data fragment 158A1 to generate a data fragment 157A, which is “00000001”, and stores the data fragment 157A in a data fragment storage unit 252A. A transmitter 251A selects the data fragment 157A from the data fragment storage unit 252A, and transmits it as a bit string 114A to the transfer apparatus 211. The lower-order 2 bits of the bit string 114A is data 141A (“01”) to be transmitted to the controller 110.
In the input/output unit 250B in FIG. 18, because an input 154B0 is ON, a data generator 253B0 generates data “11111111”, in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00000001” in which the first bit at the LSB is “1” and other bits are “0”, to generate a data fragment 158B0 (“00000001”) having an 8-bit length, in which the first bit at the LSB is “1” and other bits are “0”.
Because an input 154B1 is OFF, a data generator 253B1 generates data “00000000”, in which all 8 bits are “0”, and performs AND operation of the data and an 8-bit constant “00000010” in which the second bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158B1 (“00000000”) having an 8-bit length, in which the second bit from the LSB is “0” and other bits are “0”.
Because an input 154B2 is ON, a data generator 253B2 generates data “11111111”, in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00000100” in which the third bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158B2 (“00000100”) having an 8-bit length, in which the third bit from the LSB is “1” and other bits are “0”.
Because an input 154B3 is ON, a data generator 253B3 generates data “11111111”, in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00001000” in which the fourth bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158B3 (“00001000”) having an 8-bit length, in which the fourth bit from the LSB is “1” and other bits are “0”.
Further, a data fragment generator 256B performs OR operation of the data fragment 158B0, the data fragment 158B1, the data fragment 158B2, and the data fragment 158B3, generates a data fragment 157B, which is “00001101”, and stores the data fragment 157B in a data fragment storage unit 252B. A transmitter 251B selects the data fragment 157B from the data fragment storage unit 252B, and transmits it as a bit string 114B to the transfer apparatus 211. The low-order 4 bits in the bit string 114B is the data 141B (“1101”) to be transmitted to the controller 110.
In the input/output unit 250C in FIG. 19, because an input 154C0 is ON, a data generator 253C0 generates data “11111111”, in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00000001” in which the first bit at the LSB is “1” and other bits are “0”, to generate a data fragment 158C0 (“00000001”) having an 8-bit length, in which the first bit at the LSB is “1” and other bits are “0”.
Because an input 154C1 is OFF, a data generator 253C1 generates data “00000000”, in which all 8 bits are “0”, and performs AND operation of the data and an 8-bit constant “00000010” in which the second bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158C1 (“00000000”) having an 8-bit length, in which the second bit from the LSB is “0” and other bits are “0”.
Because an input 154C2 is ON, a data generator 253C2 generates data “11111111” in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00000100” in which the third bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158C2 (“00000100”) having an 8-bit length, in which the third bit from the LSB is “1” and other bits are “0”.
Because an input 154C3 is ON, a data generator 253C3 generates data “11111111”, in which all 8 bits are “1”, and performs AND operation of the data and an 8-bit constant “00001000” in which the fourth bit from the LSB is “1” and other bits are “0”, to generate a data fragment 158C3 (“00001000”) having an 8-bit length, in which the fourth bit from the LSB is “1” and other bits are “0”.
Further, a data fragment generator 256C performs OR operation of the data fragment 158C0, the data fragment 158C1, the data fragment 158C2, and the data fragment 158C3 to generate a data fragment 157C, which is “00001101”, and stores the data fragment 157C in a data fragment storage unit 252C. A transmitter 251C selects the data fragment 157C from the data fragment storage unit 252C, and transmits it as a bit string 114C to the transfer apparatus 211. The lower-order 4 bits of the bit string 114C is the data 141C (“1101”) to be transmitted to the controller 110.
In FIG. 16, in the transfer apparatus 211, the receiver 224 transmits the received bit string 114A as the data fragment 132A, the received bit string 114B as the data fragment 132B, and the received bit string 114C as the data fragment 132C, to the operation unit 223. The data 141A (“01”) included in the received data fragment 132A in the one-to-one correspondence in the low-order 8 bits in the bit string 113. Therefore, the operation unit 223 directly stores the data fragment 132A as the data fragment 131A in the register 223a. 
Further, the data 141B (“1101”) to be stored in the lower-order 8 bits in the string 113 included in the received data fragment 132B, but the bit positions are shifted by 2 bits. Therefore, the operation unit 223 provides the received data fragment 132B to a shift register 223b to shift the bit position by 2 bits leftward, and stores the obtained data fragment 131B, which is “00110100”, in the register 223c. 
On the other hand, because the data 141C (“1101”) included in the received data fragment 132C spans a border between the high-order 8 bits and the low-order 8 bits in the bit string 113, the operation unit 223 provides the received data fragment 132C to the shift registers 223d and 223f, so that these bits are separated from each other and the bit positions are as required.
The shift register 223d shifts data “00001101” in the data fragment 132C by 6 bits leftward, and stores the obtained data fragment 131Ca, which is “01000000”, in the register 223e. The shift register 223f shifts data “00001101” in the data fragment 132C by 2 bits rightward, and designates the obtained data fragment 131Cb, which is “00000011”, as the data fragment 228b. 
The operation unit 223 performs OR operation of the data fragment 131A stored in the register 223a, the data fragment 131B stored in the register 223c, and the data fragment 131Ca stored in the register 223e, to generate the data fragment 228a, which is “01110101”, and stores the data fragment 228a in the transmission buffer 222 as the low-order data fragment 222a. Further, the operation unit 223 stores the data fragment 228b in the transmission buffer 222 as the high-order data fragment 222b. As a result, the transmitter 221 transmits the low-order data fragment 222a and the high-order data fragment 222b to the controller 110 as the continuous bit string 113.
The process in which the transfer apparatus 211 creates the bit string 113 from the bit string 114q (q=A to C) will be specifically explained with reference to FIGS. 20 and 21. FIG. 20 illustrates a case that the transfer apparatus 211 uses an 8-bit microcomputer to execute the process. FIG. 21 is a diagram to explain details of the process related to part “c” shown in FIG. 20.
In FIG. 20, the transfer apparatus 211 defines constants in a constants defining section, declares variables in a variable defining section, initializes the variables, and stores 0x00 in the array variable d113, and obtains the value of the bit string 114q in an array variable d114 according to a function get_sensor_actuator_network_data( ). The transfer apparatus 211 then stores the value of the array variable d114[0], in which the data from an input port 154Ak (k=0, 1) in the input/output unit 250A having a station number of 1 is stored, in a variable d0, and performs OR operation of the variable d0 and the variable d113[0]. Further, the transfer apparatus 211 stores the value of the array variable d114[1], in which the data from an input port 154Bk (k=0 to 3) in the input/output unit 250B having a station number of 2 is stored, in the variable d0, shifts the value of the variable d0 by 2 bits leftward, and performs OR operation of the variable d0 and the variable d113[0].
Further, the transfer apparatus 211 stores the value of the variable d114[2], in which the data from an input port 154Ck (k=0 to 3) in the input/output unit 250C having a station number of 4 is stored, in the variable d0. After shifting the value of the variable d0 by 6 bits leftward, the transfer apparatus 211 performs OR operation of the variable d0 and the variable d113[0]. Subsequently, the transfer apparatus 211 stores the value of the variable d114[2] in the variable d0, shifts the value of the variable d0 by 2 bits rightward, and stores the value of the variable d0 in the variable d113[1]. As a result, storage of data in the array variable d113 finishes, and the transfer apparatus 211 transmits the data stored in the array variable d113 to the controller 110 according to a function of set_field_network_data ( ).
In FIG. 21, the processing for part “c” shown in FIG. 20 is shown in column (A), the processing operation actually performed by the microcomputer is shown in column (B), and the required number of clock cycles is shown in column (C). In column (C), the number of clock cycles required for the microcomputer to execute the processing for one line is expressed as 1, the number of clock cycles for lines that are not executed as a result of condition decision is expressed as 0, and the number of clock cycles for lines to be executed is expressed as 1, and the total of number of clock cycles is shown in the lowermost line.
In column (B) in FIG. 21, from step (1) to step (4), a value 0x00 stored in a variable p250q[0] is stored in a variable p0. From step (5) to step (11), because the value of p0 is 0x00, shift operation is not performed with respect to the variable d0 in which a value 0x01 is stored. From step (12) to step (18), OR operation of the value of the variable d0 and the variable d113[0] is performed, to change the value of the variable d113[0] to 0x01. From step (19) to step (23), because the value of a variable p0 is not 0x06, the value of the variable p113 is not changed. From step (24) to step (28), because the value of a variable flag_of_separate[0] is 0x00, processing of in case of q=0 is finished, and control proceeds to processing of in case of q=0. From step (41) to step (44), the value 0x02 stored in the yariable p250q[1] is stored in the variable p0. From step (45) to step (51), because the value of the variable p0 is 0x02, a value 0x0D stored in the variable d0 is shifted Ieftward by 2 bits, to obtain a value 0x34 in the variable d0.
From step (52) to step (58), OR operation of the value of the variable d0 and the variable d113[0] is performed, to change the value of the variable d113[0] to 0x35. From step (59) to step (63), because the value of the variable p0 is not 0x06, the value of the variable p113 is not changed. From step (64) to step (68), because the value of the variable flag_of_separate[1] is 0x00, processing of in case of q=1 is finished, and control proceeds to processing of in case of q=2. From step (81) to step (84), the value 0x06 stored in the variable p250q[3] is stored in the variable p0. From step (85) to step (91), because the value of the variable p0 is 0x06, a value 0x0D of the variable d0 is shifted 6 bits leftward to obtain a value 0x40in the variable d0. From step (92) to step (98), OR operation of the value of the variable d0 and the variable d113[0] is performed, to change the value of the variable d113[0] to 0x75.
From step (99) to step (103), because the value of the variable p0 is 0x06, 1 is added to the value of the variable p113. From step (104) to step (120), because the value of the variable flag_of_separate[3] is not 0x00, the value of the variable d114[2] is stored in the variable d0. A result of shifting the value of the variable d0 by 2 bits rightward is stored in the variable d113[1], to change the value of the variable d113[1] to 0x03. As a result, the process for storing the bit string 141q in the array variable d113 is complete. According to the above processing, when the required number of clock cycles per command is 1 clock cycle, as shown in column (C) in FIG. 21, a total of 116 clock cycles is required for the processing of the part “c” shown in FIG. 20.
However, according to the conventional processing method, because the bit shift operation is required when the transfer apparatus transfers data to the controller, there is a problem in that it takes time to perform the process of creating a transmission frame to be transmitted to the controller.
Because the transfer apparatus collects data from all input/output units through the sensor/actuator network, the time required until the process for collecting data from all input/output units completes is calculated by multiplying the processing time for one unit by the number of input/output units. As a result, there is a problem in that a delay in the process by the shift process causes performance deterioration in the data collection process.
The present invention has been achieved in order to solve the above problems. It is an object of the present invention to provide a data collection system, which does not require the shift operation of bits by the transfer apparatus.